1. Field of the Invention
The present invention is related to on-chip resistors for Integrated Circuit (IC) chips and more particularly to on-chip discrete resistors in Ultra-Thin SOI (UTSOI) ICs.
2. Background Description
Integrated Circuits (ICs) are commonly made in the well-known complementary insulated gate Field Effect Transistor (FET) technology known as CMOS. Typical high performance ICs include CMOS devices (FETs) formed in a number of stacked layers (e.g., wiring, via, gate and gate dielectric) on a surface semiconductor (silicon) layer of a Silicon On Insulator (SOI) chip or wafer. CMOS technology and chip manufacturing advances have resulted in a steady decrease of chip feature size to increase on-chip circuit switching frequency (circuit performance) and the number of transistors (circuit density). In what is typically referred to as scaling, device or FET features are reduced to shrink corresponding device minimum dimensions, including both horizontal dimensions (e.g., minimum channel length) and vertical dimensions, e.g., channel layer depth, gate dielectric thickness, junction depths and etc. Shrinking device size increases device density and improves circuit performance (both from increased device drive capability and decreased capacitive load). Scaling also entails thinning the surface device layer to control device threshold roll off. Especially in Ultra-Thin SOI (UTSOI), thinning the surface device layer has resulted in devices with fully-depleted bodies (i.e., in what is known as Fully-Depleted SOI or FD-SOI). Scaled FD-SOI devices can have substantially higher series resistance, as well as substantially higher capacitance in some aspects.
Frequently, a circuit requires a fixed resistance. Doped semiconductor, typically, has a relatively well-defined sheet resistance (ρ). The sheet resistance of a particular layer is given as a number of ohms per square (Ω/) that depends upon dopant concentration and layer depth. So, normally, CMOS resistors are formed by defining doped region in a chip surface or surface layer, e.g., a doped rectangle in the silicon surface layer of a SOI chip with contacts at opposite ends. The resistance for such a resistor can be determined by dividing the distance between the contacts (length) by the other rectangle dimension (width) to arrive at the number of squares and multiplying that number by the sheet resistance. Unfortunately, with the thinner layers in UTSOI, sheet resistance varies with electrical field in doped semiconductors, whether doped polysilicon or doped surface layer.
While for thicker surface layers this variation had been neglectable, UTSOI surface layers may be so thin and the sheet resistance may be so high, that a voltage on an adjacent conducting layer fully depletes the surface layer shape intended to act as resistor. Thus, although a doped silicon structure may be a planar resistor by design, it may be voltage varying or naturally free of mobile charge due to low dopant charge and surrounding built-in fields. This is because the front or top gate workfunction (from overlying structures) and the back gate (substrate) workfunction, the thinness of the channel, and the dopant limits on the thin resistor body channel, may combine to fully deplete the channel (resistor body under the gate) of mobile charge. So, the workfunction of adjacent structures to a planar resistor creates electric fields such that the planar resistor is fully-depleted even under normal bias conditions and, therefore, very high resistance.
Consequently, depending upon placement with other circuit shapes such a doped silicon shape may have a time varying (and unpredictable) resistance and under some circumstances (e.g., a doped silicon surface layer shape that is biased by adjacent bulk silicon), be so high as to act as an open circuit. Moreover, the above mentioned combination of dopant solid solubility limits and low volume may result in unusably high resistance even in moderately to highly doped regions of the UTSOI surface layer.
Thus, there is a need for well behaved on-chip resistors in UTSOI with well-defined resistance that is not voltage or time varying.